Integrated circuits are formed by repeatedly projecting a pattern in a lithographic step onto a semiconductor wafer and processing the wafer to transfer the pattern into a layer deposited on the wafer surface. Planarization and other intermediate processes may further be necessary to prepare a projection of a successive mask level.
In order to manufacture integrated circuits of increased device densities and smaller geometries large efforts have to be undertaken to guarantee sufficient alignment of patterns in different structured layers on the wafer. Quality control is performed by measuring the shifts of portions in a measurement mark that belong to a pattern of the current layer with respect to another portion of the mark that belongs to a previous layer. Typically, so-called box-in-box structures are used to quantify the amount of shift and the direction of a pattern in one layer with respect to another layer.
A measured amount of shift represents an overlay error. When performing overlay metrology in order to control the efficiency and the yield of a lithographic projection step or its post-processes, it often occurs that the measured shifts show a systematic trend with position on the wafer. For example, a signature of rotation is often discovered from modeling of the overlay error measurement results, when a polishing process has previously been applied to one of the layers under inspection.
Such systematic trends are expected in advance and a sample of measurement marks, referred to as overlay targets in what follows, is selected from a plurality of overlay targets distributed across the wafer that easily reflects such systematic trends. Sampling has become necessary because measuring the full plurality of overlay targets on a wafer would consume too much time and would reduce the throughput of wafers in a fabrication facility considerably.
However, with decreasing feature sizes of state of the art integrated circuits, arbitrary, non-systematic errors become more and more influential in the performance of the device. One example is lens aberration that leads to pattern shifts on a wafer, which depend on the particular combination of exposure apparatus employed for projecting patterns into respective layers. Another example is wafer warpage that depends on material characteristics and thermal as well as mechanical effects that have been acted upon a specific wafer.
Previous sampling methods selecting specific subsets of overlay targets across the wafer were not able to provide a good representation of the overall distribution of shifts on a wafer. Sometimes, small amounts of measured shifts determined from a small subset of overlay targets pretend a good alignment between two successively projected layers, while non-selected overlay targets positioned in other, more critical areas on a wafer would reveal large shifts if these were included in the measurement set. Accordingly, the quality of the quality control itself may disadvantageously be impacted. Since errors are therefore detected too late, e.g., in a tester step testing the integrated circuit, costs spent in damaged circuits have accumulated and the time to deliver circuits to the customer has unnecessarily increased.
It is accordingly an object of the invention to improve the quality of an overlay measurement step performed in semi-conductor manufacturing. It is a particular object to increase the accuracy of the overlay measurement results, when these are represented by measurements using sample overlay targets. It is a further object of the invention to increase the yield and reduce the costs in semi-conductor manufacturing.